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HD64F36077G 参数 Datasheet PDF下载

HD64F36077G图片预览
型号: HD64F36077G
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内容描述: 旧公司名称在产品目录等资料 [Old Company Name in Catalogs and Other Documents]
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文件页数/大小: 566 页 / 3220 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Section 12 Timer V  
12.5.2  
Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input  
The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary  
delay from the TRGV input, as shown in figure 12.10. To set up this output:  
1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with  
TCORB.  
2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA  
and to 0 at compare match with TCORB.  
3. Set bits TVEG1 and TVEG0 in TCRV1 and set TRGE to select the falling edge of the TRGV  
input.  
4. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.  
5. After these settings, a pulse waveform will be output without further software intervention,  
with a delay determined by TCORA from the TRGV input, and a pulse width determined by  
(TCORB – TCORA).  
TCNTV value  
H'FF  
Counter cleared  
TCORB  
TCORA  
H'00  
Time  
TRGV  
TMOV  
Compare match A  
Compare match B  
Compare match A  
Compare match B  
clears TCNTV and  
halts count-up  
clears TCNTV and  
halts count-up  
Figure 12.10 Example of Pulse Output Synchronized to TRGV Input  
Rev. 3.00 Sep. 10, 2007 Page 196 of 528  
REJ09B0216-0300  
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