欢迎访问ic37.com |
会员登录 免费注册
发布采购

HD64F36077G 参数 Datasheet PDF下载

HD64F36077G图片预览
型号: HD64F36077G
PDF下载: 下载PDF文件 查看货源
内容描述: 旧公司名称在产品目录等资料 [Old Company Name in Catalogs and Other Documents]
分类和应用:
文件页数/大小: 566 页 / 3220 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
 浏览型号HD64F36077G的Datasheet PDF文件第221页浏览型号HD64F36077G的Datasheet PDF文件第222页浏览型号HD64F36077G的Datasheet PDF文件第223页浏览型号HD64F36077G的Datasheet PDF文件第224页浏览型号HD64F36077G的Datasheet PDF文件第226页浏览型号HD64F36077G的Datasheet PDF文件第227页浏览型号HD64F36077G的Datasheet PDF文件第228页浏览型号HD64F36077G的Datasheet PDF文件第229页  
Section 12 Timer V  
12.3.5  
Timer Control Register V1 (TCRV1)  
TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to  
TCNTV.  
Initial  
Bit  
Bit Name Value  
R/W  
Description  
7 to 5  
All 1  
Reserved  
These bits are always read as 1.  
TRGV Input Edge Select  
4
3
TVEG1  
TVEG0  
0
0
R/W  
R/W  
These bits select the TRGV input edge.  
00: TRGV trigger input is prohibited  
01: Rising edge is selected  
10: Falling edge is selected  
11: Rising and falling edges are both selected  
2
TRGE  
0
R/W  
TCNT starts counting up by the input of the edge which is  
selected by TVEG1 and TVEG0.  
0: Disables starting counting-up TCNTV by the input of  
the TRGV pin and halting counting-up TCNTV when  
TCNTV is cleared by a compare match.  
1: Enables starting counting-up TCNTV by the input of  
the TRGV pin and halting counting-up TCNTV when  
TCNTV is cleared by a compare match.  
1
0
1
0
Reserved  
This bit is always read as 1.  
Internal Clock Select 0  
ICKS0  
R/W  
This bit selects clock signals to input to TCNTV in  
combination with CKS2 to CKS0 in TCRV0.  
Refer to table 12.2.  
Rev. 3.00 Sep. 10, 2007 Page 191 of 528  
REJ09B0216-0300  
 复制成功!