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HD64F36077G 参数 Datasheet PDF下载

HD64F36077G图片预览
型号: HD64F36077G
PDF下载: 下载PDF文件 查看货源
内容描述: 旧公司名称在产品目录等资料 [Old Company Name in Catalogs and Other Documents]
分类和应用:
文件页数/大小: 566 页 / 3220 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Section 12 Timer V  
12.2  
Input/Output Pins  
Table 12.1 shows the timer V pin configuration.  
Table 12.1 Pin Configuration  
Name  
Abbreviation I/O  
Function  
Timer V output  
Timer V clock input  
Timer V reset input  
Trigger input  
TMOV  
TMCIV  
TMRIV  
TRGV  
Output  
Input  
Input  
Input  
Timer V waveform output  
Clock input to TCNTV  
External input to reset TCNTV  
Trigger input to initiate counting  
12.3  
Register Descriptions  
Time V has the following registers.  
Timer counter V (TCNTV)  
Timer constant register A (TCORA)  
Timer constant register B (TCORB)  
Timer control register V0 (TCRV0)  
Timer control/status register V (TCSRV)  
Timer control register V1 (TCRV1)  
12.3.1  
Timer Counter V (TCNTV)  
TCNTV is an 8-bit up-counter. The clock source is selected by bits CKS2 to CKS0 in timer  
control register V0 (TCRV0). The TCNTV value can be read and written by the CPU at any time.  
TCNTV can be cleared by an external reset input signal, or by compare match A or B. The  
clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0.  
When TCNTV overflows, OVF is set to 1 in timer control/status register V (TCSRV).  
TCNTV is initialized to H'00.  
Rev. 3.00 Sep. 10, 2007 Page 187 of 528  
REJ09B0216-0300  
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