Table 2.8 lists the SH7709S logic operation instructions.
Table 2.8 Logic Operation Instructions
Privileged
Mode Cycles T Bit
Instruction
Operation
Code
AND
AND
Rm,Rn
#imm,R0
Rn & Rm → Rn
R0 & imm → R0
0010nnnnmmmm1001
11001001iiiiiiii
11001101iiiiiiii
—
—
—
1
1
3
—
—
—
AND.B #imm,@(R0,GBR)
(R0 + GBR) & imm →
(R0 + GBR)
NOT
OR
Rm,Rn
~Rm → Rn
0110nnnnmmmm0111
0010nnnnmmmm1011
11001011iiiiiiii
11001111iiiiiiii
—
—
—
—
1
1
1
3
—
—
—
—
Rm,Rn
Rn | Rm → Rn
R0 | imm → R0
OR
#imm,R0
OR.B #imm,@(R0,GBR)
(R0 + GBR) | imm →
(R0 + GBR)
TAS.B @Rn
If (Rn) is 0, 1 → T;
1 → MSB of (Rn)
0100nnnn00011011
0010nnnnmmmm1000
11001000iiiiiiii
11001100iiiiiiii
—
—
—
—
3
1
1
3
Test
result
TST
TST
Rm,Rn
Rn & Rm; if the result
Test
is 0, 1 → T
result
#imm,R0
R0 & imm; if the result
Test
is 0, 1 → T
result
TST.B #imm,@(R0,GBR)
(R0 + GBR) & imm;
Test
if the result is 0, 1 → T
result
XOR
XOR
Rm,Rn
Rn ^ Rm → Rn
R0 ^ imm → R0
0010nnnnmmmm1010
11001010iiiiiiii
11001110iiiiiiii
—
—
—
1
1
3
—
—
—
#imm,R0
XOR.B #imm,@(R0,GBR)
(R0 + GBR) ^ imm →
(R0 + GBR)
Rev. 5.00, 09/03, page 44 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
