Privileged
Mode Cycles T Bit
Instruction
Operation
Code
LDC.L @Rm+,
(Rm) → R6_BANK,
Rm + 4 → Rm
0100mmmm11100111
√
5
—
R6_BANK
LDC.L @Rm+,
R7_BANK
(Rm) → R7_BANK,
Rm + 4 → Rm
0100mmmm11110111
√
5
—
LDS
LDS
LDS
Rm,MACH
Rm,MACL
Rm,PR
Rm → MACH
Rm → MACL
Rm → PR
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
—
—
—
—
—
—
√
1
1
1
1
1
1
1
1
2
4
—
—
—
—
—
—
—
—
—
—
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
LDS.L @Rm+,PR
LDTLB
(Rm) → MACH, Rm + 4 → Rm 0100mmmm00000110
(Rm) → MACL, Rm + 4 → Rm
(Rm) → PR, Rm + 4 → Rm
PTEH/PTEL → TLB
No operation
0100mmmm00010110
0100mmmm00100110
0000000000111000
0000000000001001
0000mmmm10000011
0000000000101011
NOP
—
—
√
PREF @Rm
RTE
(Rm) → cache
Delayed branch,
SSR → SR, SPC → PC
SETS
SETT
SLEEP
1 → S
0000000001011000
0000000000011000
0000000000011011
0000nnnn00000010
0000nnnn00010010
0000nnnn00100010
0000nnnn00110010
0000nnnn01000010
0000nnnn10000010
0000nnnn10010010
0000nnnn10100010
0000nnnn10110010
0000nnnn11000010
0000nnnn11010010
0000nnnn11100010
0000nnnn11110010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
—
—
√
1
1
4
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
—
1
1 → T
*
Sleep
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STC
STC
STC
STC
STC
STC
STC
STC
STC
STC
STC
STC
STC
SR,Rn
SR → Rn
GBR → Rn
VBR → Rn
SSR → Rn
SPC → Rn
√
GBR,Rn
VBR,Rn
SSR,Rn
SPC,Rn
—
√
√
√
R0_BANK,Rn R0_BANK→ Rn
R1_BANK,Rn R1_BANK→ Rn
R2_BANK,Rn R2_BANK→ Rn
R3_BANK,Rn R3_BANK→ Rn
R4_BANK,Rn R4_BANK→ Rn
R5_BANK,Rn R5_BANK→ Rn
R6_BANK,Rn R6_BANK→ Rn
R7_BANK,Rn R7_BANK→ Rn
√
√
√
√
√
√
√
√
STC.L SR,@–Rn
STC.L GBR,@–Rn
STC.L VBR,@–Rn
Rn–4 → Rn, SR → (Rn)
Rn–4 → Rn, GBR → (Rn)
Rn–4 → Rn, VBR → (Rn)
√
—
√
Note: * The number of cycles until the sleep state is entered.
Rev. 5.00, 09/03, page 48 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
