Privileged
Mode Cycles T Bit
Instruction
Operation
Code
*
DMULS.LRm,Rn
Signed operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
0011nnnnmmmm1101
—
2(to 5)
—
*
DMULU.LRm,Rn
Unsigned operation of
Rn × Rm → MACH,
0011nnnnmmmm0101
—
2(to 5)
—
MACL 32 × 32 → 64 bits
DT
Rn
Rn – 1 → Rn, if Rn =
0, 1 → T, else 0 → T
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
—
—
—
—
—
—
1
Comparison
result
EXTS.B Rm,Rn
EXTS.W Rm,Rn
EXTU.B Rm,Rn
EXTU.W Rm,Rn
A byte in Rm is sign-
extended → Rn
1
—
—
—
—
—
A word in Rm is sign-
1
extended → Rn
A byte in Rm is zero-
1
extended → Rn
A word in Rm is zero-
extended → Rn
1
*
*
MAC.L @Rm+,@Rn+ Signed operation of (Rn) 0000nnnnmmmm1111
2(to 5)
× (Rm) + MAC → MAC,
Rn + 4 → Rn,
Rm + 4 → Rm,
32 × 32 + 64 → 64 bits
MAC.W @Rm+,@Rn+ Signed operation of (Rn) 0100nnnnmmmm1111
—
2(to 5)
—
× (Rm) + MAC → MAC,
Rn + 2 → Rn,
Rm + 2 → Rm,
16 × 16 + 64 → 64 bits
*
*
MUL.L Rm,Rn
MULS.W Rm,Rn
Rn × Rm → MACL,
32 × 32 → 32 bits
0000nnnnmmmm0111
0010nnnnmmmm1111
—
—
2(to 5)
1(to 3)
—
—
Signed operation of Rn
× Rm → MACL,
16 × 16 → 32 bits
*
MULU.W Rm,Rn
Unsigned operation of
Rn × Rm → MACL,
16 × 16 → 32 bits
0010nnnnmmmm1110
—
1(to 3)
—
Rev. 5.00, 09/03, page 42 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
