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HD6417709SF133B 参数 Datasheet PDF下载

HD6417709SF133B图片预览
型号: HD6417709SF133B
PDF下载: 下载PDF文件 查看货源
内容描述: 瑞萨32位RISC单片机超级RISC引擎族/ SH7700系列 [Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 807 页 / 4409 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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2.3.2  
Addressing Modes  
Addressing modes and effective address calculation methods are shown in table 2.2.  
Table 2.2 Addressing Modes and Effective Addresses  
Addressing Instruction  
Mode  
Format  
Effective Address Calculation Method  
Calculation Formula  
Register direct Rn  
Effective address is register Rn. (Operand is  
register Rn contents.)  
Register  
indirect  
@Rn  
Effective address is register Rn contents.  
Rn  
Rn  
Rn  
Register  
indirect with  
post-increment  
@Rn+  
Effective address is register Rn contents. A  
constant is added to Rn after instruction  
execution: 1 for a byte operand, 2 for a word  
operand, 4 for a longword operand.  
Rn  
After instruction  
execution  
Byte: Rn + 1 Rn  
Rn  
Rn  
Word: Rn + 2 Rn  
Longword: Rn + 4 Rn  
Rn + 1/2/4  
+
1/2/4  
Register  
indirect with  
pre-decrement  
@–Rn  
Effective address is register Rn contents,  
decremented by a constant beforehand: 1 for  
a byte operand, 2 for a word operand, 4 for a  
longword operand.  
Byte: Rn – 1 Rn  
Word: Rn – 2 Rn  
Longword: Rn – 4 Rn  
(Instruction executed  
with Rn after  
Rn  
calculation)  
Rn 1/2/4  
Rn 1/2/4  
1/2/4  
Rev. 5.00, 09/03, page 28 of 760  
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