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HD6417709SF133B 参数 Datasheet PDF下载

HD6417709SF133B图片预览
型号: HD6417709SF133B
PDF下载: 下载PDF文件 查看货源
内容描述: 瑞萨32位RISC单片机超级RISC引擎族/ SH7700系列 [Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 807 页 / 4409 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Section 11 Direct Memory Access Controller (DMAC)  
11.1  
Overview  
The SH7709S includes a four-channel direct memory access controller (DMAC). The DMAC can  
be used in place of the CPU to perform high-speed transfers between external devices that have  
DACK (transfer request acknowledge signal), external memory, memory-mapped external  
devices, and on-chip peripheral modules (IrDA, SCIF, A/D converter, and D/A converter). Using  
the DMAC reduces the burden on the CPU and increases overall operating efficiency.  
11.1.1 Features  
The DMAC has the following features.  
Four channels  
4-GB address space in the architecture  
16-byte transfer (In 16-byte transfer, four 32-bit reads are executed, followed by four 32-bit  
writes.)  
Choice of 8-bit, 16-bit, 32-bit, or 16-byte transfer data length  
16 Mbytes (16,777,216 transfers)  
Address mode: Dual address mode and single address mode are supported. In addition, direct  
address transfer mode or indirect address transfer mode can be selected.  
Dual address mode transfer: Both the transfer source and transfer destination are accessed  
by address. Dual address mode has direct address transfer mode and indirect address  
transfer mode.  
Direct address transfer mode: The values specified in the DMAC registers indicates the  
transfer source and transfer destination. Two bus cycles are required for one data transfer.  
Indirect address transfer mode: Data is transferred with the address stored prior to the  
address specified in the transfer source address in the DMAC. Other operations are the  
same as those of direct address transfer mode. This function is only available in channel 3.  
Four bus cycles are required for one data transfer.  
Single address mode transfer: Either the transfer source or transfer destination peripheral  
device is accessed (selected) by means of the DACK signal, and the other device is  
accessed by address. One transfer unit of data is transferred in one bus cycle.  
Channel functions: The transfer mode that can be specified depends on the channel:  
Channel 0: External request can be accepted.  
Channel 1: External request can be accepted.  
Channel 2: This channel has a source address reload function, which reloads a source  
address every four transfers.  
Rev. 5.00, 09/03, page 327 of 760  
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