Table 10.15 MCSCRx Settings and MCS[x] Assertion Conditions (x: 0–7)
MCSCRx Settings
MCS[x] Assertion Conditions
CS2/0 CAP1 CAP0 A25 A24 A23 A22
CS0 CS2 Address Bus A [25:0]
Notes
0
1
1
0
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
—
—
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H'0000000 to H'1FFFFFF 256-Mbit ROM
H'2000000 to H'3FFFFFF
H'0000000 to H'0FFFFFF 128-Mbit ROM
H'1000000 to H'1FFFFFF
H'2000000 to H'2FFFFFF
H'3000000 to H'3FFFFFF
H'0000000 to H'07FFFFF 64-Mbit ROM
H'0800000 to H'0FFFFFF
H'1000000 to H'17FFFFF
H'1800000 to H'1FFFFFF
H'2000000 to H'27FFFFF
H'2800000 to H'2FFFFFF
H'3000000 to H'37FFFFF
H'3800000 to H'3FFFFFF
H'0000000 to H'03FFFFF 32-Mbit ROM
H'0400000 to H'07FFFFF
H'0800000 to H'0BFFFFF
H'0C00000 to H'0FFFFFF
H'1000000 to H'13FFFFF
H'1400000 to H'17FFFFF
H'1800000 to H'1BFFFFF
H'1C00000 to H'1FFFFFF
H'2000000 to H'23FFFFF
H'2400000 to H'27FFFFF
H'2800000 to H'2BFFFFF
H'2C00000 to H'2FFFFFF
H'3000000 to H'33FFFFF
H'3400000 to H'37FFFFF
H'3800000 to H'3BFFFFF
H'3C00000 to H'3FFFFFF
1
0
0
1
1
0
1
0
1
0
1
0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Rev. 5.00, 09/03, page 324 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
