Bits 15 to 13—Area 6 Wait Control (A6W2, A6W1, A6W0): Specify the number of wait states
inserted in physical space area 6. Also specify the number of states for burst transfer.
Description
Burst Cycle
First Cycle
(Excluding First Cycle)
Number of States
Per Data Transfer WAIT Pin
Bit 15: Bit 14: Bit 13: Inserted
A6W2
A6W1
A6W0
Wait States
WAIT Pin
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
0
0
0
1
0
1
0
1
0
1
0
1
2
3
4
6
8
2
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
2
1
0
1
3
4
1
4
6
8
10
10
(Initial value)
Bits 12 to 10—Area 5 Wait Control (A5W2, A5W1, A5W0): Specify the number of wait states
inserted in physical space area 5. Also specify the number of states for burst transfer.
Description
Burst Cycle
(Excluding First Cycle)
Number of States
Per Data Transfer WAIT Pin
First Cycle
Bit 12: Bit 11: Bit 10: Inserted
A5W2
A5W1
A5W0
Wait States
WAIT Pin
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
0
0
0
1
0
1
0
1
0
1
0
1
2
3
4
6
8
2
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
2
1
0
1
3
4
1
4
6
8
10
10
(Initial value)
Rev. 5.00, 09/03, page 242 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
