10.1.4
Register Configuration
The BSC has 21 registers (table 10.2). Synchronous DRAM also has a built-in synchronous
DRAM mode register. These registers control direct connection interfaces to memory, wait states,
and refreshes devices.
Table 10.2 BSC Registers
*
Name
Abbr.
BCR1
BCR2
WCR1
WCR2
MCR
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value Address
Bus Width
Bus control register 1
Bus control register 2
Wait state control register 1
Wait state control register 2
H'0000
H'3FF0
H'3FF3
H'FFFF
H'0000
H'FFFFFF60
16
16
16
16
16
H'FFFFFF62
H'FFFFFF64
H'FFFFFF66
H'FFFFFF68
Individual memory control
register
PCMCIA control register
PCR
R/W
R/W
H'0000
H'0000
H'FFFFFF6C 16
H'FFFFFF6E 16
Refresh timer control/status
register
RTCSR
Refresh timer counter
RTCNT
RTCOR
RFCR
R/W
R/W
R/W
W
H'0000
H'0000
H'0000
—
H'FFFFFF70
H'FFFFFF72
H'FFFFFF74
16
16
16
8
Refresh time constant register
Refresh count register
Synchronous DRAM mode
register, area 2
SDMR
H'FFFFD000–
H'FFFFDFFF
Synchronous DRAM mode
register, area 3
H'FFFFE000–
H'FFFFEFFF
MCS0 control register
MCS1 control register
MCS2 control register
MCS3 control register
MCS4 control register
MCS5 control register
MCS6 control register
MCS7 control register
MCSCR0 R/W
MCSCR1 R/W
MCSCR2 R/W
MCSCR3 R/W
MCSCR4 R/W
MCSCR5 R/W
MCSCR6 R/W
MCSCR7 R/W
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'FFFFFF50
H'FFFFFF52
H'FFFFFF54
H'FFFFFF56
H'FFFFFF58
16
16
16
16
16
H'FFFFFF5A 16
H'FFFFFF5C 16
H'FFFFFF5E 16
Notes: For details, see section 10.2.7, Synchronous DRAM Mode Register (SDMR).
* Initialized by a power-on reset.
Rev. 5.00, 09/03, page 228 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
