10.1.2 Block Diagram
Figure 10.1 shows a block diagram of the bus state controller.
Bus
interface
WCR1
Wait
controller
WAIT
WCR2
CS0, CS6 to CS2,
CE2A, CE2B
MCS0 to MCS7
Area
controller
BCR1
BCR2
BS
RD
RD/WR
MCR
PCR
WE3 to WE0
RASxx
CASx
Memory
controller
CKE
ICIORD, ICIOWR
MCSCRn
RFCR
IOIS16
RTCNT
Refresh
controller
Interrupt
controller
Comparator
RTCOR
RTCSR
BSC
Legend
WCR:
BCR:
MCR:
PCR:
RFCR:
RTCNT:
RTCOR:
RTCSR:
MCSCRn:
Wait state control register
Bus control register
Memory control register
PCMCIA control register
Refresh count register
Refresh timer count register
Refresh time constant register
Refresh timer control/status register
MCSn control register (n = 0−7)
Figure 10.1 Block Diagram of Bus State Controller
Rev. 5.00, 09/03, page 225 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
