7.2.11
Branch Source Register (BRSR)
BRSR is a 32-bit read register. BRSR stores the last fetched address before branch and the pointer
(3 bits) which indicates the number of cycles from fetch to execution for the last executed
instruction. BRSR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0,
when BRSR is read and also initialized by power-on resets or manual resets. Other bits are not
initialized by reset. Eight BRSR registers have queue structure and a stored register is shifted
every branch.
Bit:
31
SVF
0
30
PID2
*
29
PID1
*
28
PID0
*
27
26
25
24
BSA27 BSA26 BSA25 BSA24
Initial value:
R/W:
*
*
*
*
R
R
R
R
R
R
R
R
Bit:
23
22
21
20
19
18
17
16
BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16
Initial value:
R/W:
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
Bit:
15
14
13
12
11
10
9
BSA9
*
8
BSA8
*
BSA15 BSA14 BSA13 BSA12 BSA11 BSA10
Initial value:
R/W:
*
*
*
*
*
*
R
R
R
R
R
R
R
R
Bit:
7
BSA7
*
6
BSA6
*
5
BSA5
*
4
BSA4
*
3
BSA3
*
2
BSA2
*
1
BSA1
*
0
BSA0
*
Initial value:
R/W:
R
R
R
R
R
R
R
R
Note: * Undefined value
Bit 31—BRSR Valid Flag (SVF): Indicates whether the address and the pointer by which the
branch source address can be calculated. When a branch source address is fetched, this flag is set
to 1. This flag is cleared to 0 in reading BRSR.
Bit 31: SVF
Description
0
1
The value of BRSR register is invalid
The value of BRSR register is valid
Rev. 5.00, 09/03, page 167 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
