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HD6417709SF133B 参数 Datasheet PDF下载

HD6417709SF133B图片预览
型号: HD6417709SF133B
PDF下载: 下载PDF文件 查看货源
内容描述: 瑞萨32位RISC单片机超级RISC引擎族/ SH7700系列 [Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 807 页 / 4409 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Bit 21—Break ASID Mask A (BASMA): Specifies whether the bits of the channel A break  
ASID7-ASID0 (BASA7 to BASA0) set in BASRA are masked or not.  
Bit 21: BASMA Description  
0
1
All BASRA bits are included in break condition, ASID is checked  
(Initial value)  
No BASRA bits are included in break condition, ASID is not checked  
Bit 20—Break ASID Mask B (BASMB): Specifies whether the bits of channel B break ASID7-  
ASID0 (BASB7 to BASB0) set in BASRB are masked or not.  
Bit 20: BASMB Description  
0
1
All BASRB bits are included in break condition, ASID is checked  
(Initial value)  
No BASRB bits are included in break condition, ASID is not checked  
Bits 19 to 16—Reserved: These bits are always read as 0. The write value should always be 0.  
Bit 15—CPU Condition Match Flag A (SCMFCA): When the CPU bus cycle condition in the  
break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to  
clear this flag, write 0 into this bit.  
Bit 15:  
SCMFCA  
Description  
0
1
The CPU cycle condition for channel A does not match  
The CPU cycle condition for channel A matches  
(Initial value)  
Bit 14—CPU Condition Match Flag B (SCMFCB): When the CPU bus cycle condition in the  
break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to  
clear this flag, write 0 into this bit.  
Bit 14:  
SCMFCB  
Description  
0
1
The CPU cycle condition for channel B does not match  
The CPU cycle condition for channel B matches  
(Initial value)  
Rev. 5.00, 09/03, page 163 of 760  
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