Bits 30 to 28—Instruction Decode Pointer (PID2 to PID0): PID is a 3-bit binary pointer (0–7).
These bits indicate the instruction buffer number which stores the last executed instruction before
branch.
Bits 30 to 28:
PID
Description
Even
Odd
PID indicates the instruction buffer number.
PiD+2 indicates the instruction buffer number
Bits 27 to 0—Branch Source Address (BSA27 to BSA0): These bits store the last fetched
address before branch.
7.2.12 Branch Destination Register (BRDR)
BRDR is a 32-bit read register. BRDR stores the branch destination fetch address. BRDR has the
flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRDR is read and
also initialized by power-on resets or manual resets. Other bits are not initialized by resets. Eight
BRDR registers have queue structure and a stored register is shifted every branch.
Bit:
31
DVF
0
30
—
*
29
—
*
28
—
*
27
26
25
24
BDA27 BDA26 BDA25 BDA24
Initial value:
R/W:
*
*
*
*
R
R
R
R
R
R
R
R
Bit:
23
22
21
20
19
18
17
16
BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16
Initial value:
R/W:
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
Bit:
15
14
13
12
11
10
9
BDA9
*
8
BDA8
*
BDA15 BDA14 BDA13 BDA12 BDA11 BDA10
Initial value:
R/W:
*
*
*
*
*
*
R
R
R
R
R
R
R
R
Bit:
7
BDA7
*
6
BDA6
*
5
BDA5
*
4
BDA4
*
3
BDA3
*
2
BDA2
*
1
BDA1
*
0
BDA0
*
Initial value:
R/W:
R
R
R
R
R
R
R
R
Note: * Undefined value
Rev. 5.00, 09/03, page 168 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
