Table 6.8 Interrupt Response Time
Number of States
PINT
Peripheral
Modules
Item
NMI
IRQ
Notes
Time for priority
decision and SR
mask bit comparison + 0.5 × Pcyc + 4.5 ×
0.5 × Icyc
+ 0.5 × Bcyc + 1 × Bcyc
0.5 × Icyc
0.5 × Icyc
+ 3.5 × Pcyc + 1.5 ×
0.5 × Icyc
5
*
Pcyc
4
*
Pcyc
0.5 × Icyc
6
*
+ 3 × Pcyc
Wait time until end
of sequence being
executed by CPU
X (≥ 0) × Icyc X (≥ 0) × Icyc X (≥ 0) × Icyc X (≥ 0) × Icyc Interrupt exception
handling is kept
waiting until the
executing instruc-
tion ends. If the
number of instruc-
tion execution
states is S*1, the
maximum wait
time is: X = S – 1.
However, if BL is
set to 1 by instru-
ction execution or
by an exception,
interrupt exception
handling is
deferred until
completion of an
instruction that
clears BL to 0. If
the following
instruction masks
interrupt exception
handling, the
handling may be
further deferred.
Time from interrupt
exception handling
(save of SR and PC)
until fetch of first
instruction of
5 × Icyc
5 × Icyc
5 × Icyc
5 × Icyc
exception handler is
started
Rev. 5.00, 09/03, page 146 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
