Program
execution state
Yes
ICR1.MAI = 1?
No
No
NMI = low?
No
Yes
Interrupt
generated?
Yes
No
ICR1.BLMSK = 1?
Yes
SR.BL= 0
or sleep mode?
No
Yes
NMI?
Yes
No
No
NMI?
Yes
No
Level 15
interrupt?
Yes
No
Level 14
interrupt?
IRQOUT = low
I3−I0 level
14 or lower?
Yes
Yes
No
Level 1
interrupt?
Set interrupt cause in
INTEVT, INTEVT2
No
I3−I0 level
13 or lower?
Yes
Yes
Save SR to SSR;
save PC to SPC
No
I3−I0
level 0?
Yes
No
Set BL/MD/RB
bits in SR to 1
Branch to exception
handler
I3−I0: Interrupt mask bits in status register (SR)
Figure 6.3 Interrupt Operation Flowchart
Rev. 5.00, 09/03, page 144 of 760