6.4.2
Multiple Interrupts
When handling multiple interrupts, an interrupt handler should include the following procedures:
1. Branch to a specific interrupt handler corresponding to a code set in INTEVT and INTEVT2.
The code in INTEVT and INTEVT2 can be used as a branch-offset for branching to the
specific handler.
2. Clear the cause of the interrupt in each specific handler.
3. Save SSR and SPC to memory.
4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR.
5. Handle the interrupt.
6. Execute the RTE instruction.
When these procedures are followed in order, an interrupt of higher priority than the one being
handled can be accepted after clearing BL in step 4. Figure 6.3 shows a sample interrupt operation
flowchart.
6.5
Interrupt Response Time
The time from generation of an interrupt request until interrupt exception handling is performed
and fetching of the first instruction of the exception handler is started (the interrupt response time)
is shown in table 6.8. Figure 6.4 shows an example of pipeline operation when an IRL interrupt is
accepted. When SR.BL is 1, interrupt exception handling is masked, and is kept waiting until
completion of an instruction that clears BL to 0.
Rev. 5.00, 09/03, page 145 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
