Table 6.5 Interrupt Exception Handling Sources and Priority (IRL Mode)
Interrupt
Priority
(Initial Value) Numbers)
Priority
within IPR Default
Setting Unit Priority
INTEVT Code
(INTEVT2 Code)
IPR (Bit
Interrupt Source
NMI
H'1C0 (H'1C0)
H'5E0 (H'5E0)
IRL(3:0) 2 = 0000 H'200 (H'200)
16
15
15
14
13
12
11
10
9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
High
UDI
—
*
IRL
—
2
*
IRL(3:0) = 0001 H'220 (H'220)
—
IRL(3:0) 2 = 0010 H'240 (H'240)
—
*
2
*
IRL(3:0) = 0011 H'260 (H'260)
—
IRL(3:0) 2 = 0100 H'280 (H'280)
—
*
IRL(3:0) 2 = 0101 H'2A0 (H'2A0)
—
*
IRL(3:0) 2 = 0110 H'2C0 (H'2C0)
—
*
IRL(3:0) 2 = 0111 H'2E0 (H'2E0)
8
—
*
IRL(3:0) 2 = 1000 H'300 (H'300)
7
—
*
IRL(3:0) 2 = 1001 H'320 (H'320)
6
—
*
IRL(3:0) 2 = 1010 H'340 (H'340)
5
—
*
IRL(3:0) 2 = 1011 H'360 (H'360)
4
—
*
IRL(3:0) 2 = 1100 H'380 (H'380)
3
—
*
IRL(3:0) 2 = 1101 H'3A0 (H'3A0)
2
—
*
IRL(3:0) 2 = 1110 H'3C0 (H'3C0)
1
—
*
H'200–3C0 1 (H'680) 0–15 (0)
IPRD (3–0)
IPRD (7–4)
*
IRQ
IRQ4
*
IRQ5
H'200–3C0 1 (H'6A0) 0–15 (0)
H'200–3C0 1 (H'700) 0–15 (0)
IPRD (15–12) —
IPRD (11–8)
*
PINT PINT0–7
PINT8–15
DMAC DEI0
DEI1
H'200–3C0 1 (H'720) 0–15 (0)
—
*
H'200–3C0 1 (H'800) 0–15 (0)
IPRE (15–12) High
*
H'200–3C0 1 (H'820)
*
H'200–3C0 1 (H'840)
*
DEI2
H'200–3C0 1 (H'860)
Low
*
DEI3
H'200–3C0 1 (H'880) 0–15 (0)
IPRE (11–8) High
*
IrDA
ERI1
RXI1
BRI1
TXI1
H'200–3C0 1 (H'8A0)
*
H'200–3C0 1 (H'8C0)
*
H'200–3C0 1 (H'8E0)
Low
Low
*
Rev. 5.00, 09/03, page 128 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
