6.3.2
Interrupt Control Register 0 (ICR0)
ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and
indicates the input signal level at the NMI pin. This register is initialized to H'0000 or H'8000 by a
power-on reset or manual reset, but is not initialized in standby mode.
Bit:
15
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
NMIE
0
NMIL
*
Initial value:
R/W:
0/1
R
R
R
R
R
R
R
R/W
Bit:
7
6
—
0
5
—
0
4
—
0
3
—
0
2
—
0
1
—
0
0
—
0
—
0
Initial value:
R/W:
R
R
R
R
R
R
R
R
Note: * 1 when NMI input is high, 0 when NMI input is low.
Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can
be read to determine the NMI pin level. This bit cannot be modified.
Bit 15: NMIL
Description
0
1
NMI input level is low
NMI input level is high
Bit 8—NMI Edge Select (NMIE): Selects whether the falling or rising edge of the interrupt
request signal at the NMI pin is detected.
Bit 8: NMIE
Description
0
1
Interrupt request is detected on falling edge of NMI input
Interrupt request is detected on rising edge of NMI input
Bits 14 to 9 and 7 to 0—Reserved: These bits are always read as 0. The write value should
always be 0.
Rev. 5.00, 09/03, page 132 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
