Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode)
Interrupt
Priority
(Initial Value) Numbers)
Priority
within IPR Default
Setting Unit Priority
INTEVT Code
(INTEVT2 Code)
IPR (Bit
Interrupt Source
NMI
UDI
H'1C0 (H'1C0)
H'5E0 (H'5E0)
16
15
—
—
—
—
—
—
High
—
*
IRQ
IRQ0
H'200–3C0 (H'600) 0–15 (0)
IPRC (3–0)
IPRC (7–4)
IPRC (11–8)
*
H'200–3C0 (H'620) 0–15 (0)
IRQ1
*
H'200–3C0 (H'640) 0–15 (0)
IRQ2
*
IRQ3
H'200–3C0 (H'660) 0–15 (0)
IPRC (15–12) —
*
IRQ4
H'200–3C0 (H'680) 0–15 (0)
IPRD (3–0)
IPRD (7–4)
—
—
*
H'200–3C0 (H'6A0) 0–15 (0)
IRQ5
*
PINT
PINT0–7
PINT8–15
H'200–3C0 (H'700) 0–15 (0)
IPRD (15–12) —
IPRD (11–8)
*
H'200–3C0 (H'720) 0–15 (0)
—
*
DMAC DEI0
DEI1
H'200–3C0 (H'800) 0–15 (0)
IPRE (15–12) High
*
H'200–3C0 (H'820)
*
H'200–3C0 (H'840)
DEI2
*
DEI3
H'200–3C0 (H'860)
Low
*
IrDA
SCIF
ADC
ERI1
RXI1
BRI1
TXI1
ERI2
RXI2
BRI2
TXI2
ADI
H'200–3C0 (H'880) 0–15 (0)
IPRE (11–8) High
*
H'200–3C0 (H'8A0)
*
H'200–3C0 (H'8C0)
*
H'200–3C0 (H'8E0)
Low
*
H'200–3C0 (H'900) 0–15 (0)
IPRE (7–4)
IPRE (3–0)
High
*
H'200–3C0 (H'920)
*
H'200–3C0 (H'940)
*
H'200–3C0 (H'960)
Low
—
*
H'200–3C0 (H'980) 0–15 (0)
TMU0 TUNI0
TMU1 TUNI1
TMU2 TUNI2
TICPI2
H'400 (H'400)
H'420 (H'420)
H'440 (H'440)
H'460 (H'460)
0–15 (0)
0–15 (0)
0–15 (0)
IPRA (15–12) —
IPRA (11–8)
IPRA (7–4)
—
High
Low
Low
Rev. 5.00, 09/03, page 126 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
