Interrupt
Priority
(Initial Value) Numbers)
Priority
within IPR Default
Setting Unit Priority
INTEVT Code
(INTEVT2 Code)
IPR (Bit
Interrupt Source
SCIF ERI2
RXI2
H'200–3C0 1 (H'900) 0–15 (0)
IPRE (7–4)
High
High
*
H'200–3C0 1 (H'920)
*
H'200–3C0 1 (H'940)
*
BRI2
H'200–3C0 1 (H'960)
Low
—
*
TXI2
H'200–3C0 1 (H'980) 0–15 (0)
IPRE (3–0)
*
ADC ADI
TMU0 TUNI0
TMU1 TUNI1
TMU2 TUNI2
TICPI2
H'400 (H'400)
H'420 (H'420)
H'440 (H'440)
H'460 (H'460)
H'480 (H'480)
H'4A0 (H'4A0)
H'4C0 (H'4C0)
H'4E0 (H'4E0)
H'500 (H'500)
H'520 (H'520)
H'540 (H'540)
H'560 (H'560)
H'580 (H'580)
H'5A0 (H'5A0)
0–15 (0)
0–15 (0)
0–15 (0)
IPRA (15–12) —
IPRA (11–8)
IPRA (7–4)
—
High
Low
High
RTC
ATI
PRI
CUI
ERI
RXI
TXI
TEI
0–15 (0)
0–15 (0)
IPRA (3–0)
IPRB (7–4)
Low
SCI
High
Low
WDT ITI
REF RCMI
ROVI
0–15 (0)
0–15 (0)
IPRB (15–12) —
IPRB (11–8) High
Low
Low
Notes: 1. The code corresponding to an interrupt level shown in table 6.6 is set.
2. When IRLS3–IRLS0 are enabled, IRL is the higher level of IRL3–IRL0 and IRLS3–
IRLS0.
Rev. 5.00, 09/03, page 129 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
