•
SPC when exception occurs: The PC saved to SPC when an exception occurs is as shown
below:
Re-executing-type exceptions: PC of the instruction that caused the exception is set in SPC
and re-executed after return from exception handling. If the exception occurred in a delay
slot, however, PC of the immediately prior delayed branch instruction is set in SPC. If the
condition of the conditional delayed branch instruction is not satisfied, the delay slot PC is
set in SPC.
Completed-type exceptions and interrupts: PC of the instruction after the one that caused
the exception is set in SPC. If the exception was caused by a conditional delayed branch
instruction, however, the branch destination PC is set in SPC. If the condition of the
conditional delayed branch instruction is not satisfied, the delay slot PC is set in SPC.
•
Initial register values after reset
Undefined registers
R0_BANK0/1–R7_BANK0/1, R8–R15, GBR, SPC, SSR, MACH, MACL, PR
Initialized registers
VBR = H'00000000
SR.MD = 1, SR.BL = 1, SR.RB = 1, SR.I3–SR.I0 = H'F. Other SR bits are undefined.
PC = H'A0000000
•
•
Ensure that an exception is not generated at an RTE instruction delay slot, as operation is not
guaranteed in this case.
When the BL bit in the SR register is set to 1, ensure that a TLB-related exception or address
error does not occur at an LDC instruction that updates the SR register and the following
instruction. This will be identified as the occurrence of multiple exceptions, and may initiate
reset processing.
Rev. 5.00, 09/03, page 101 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
