Pipeline Sequence:
Instruction n
IF
ID
IF
EX
ID
MA
WB
TLB miss (data access)
Instruction n + 1
EX
MA
WB
TLB miss (instruction access)
Instruction n + 2
IF
ID
EX
MA
WB
RIE (reserved instruction exception)
Detection Order:
TLB miss (instruction n+1)
TLB miss (instruction n) and general illegal instruction exception (instruction n + 2)
= simultaneous detection
Handling Order:
Program Order:
TLB miss (instruction n)
1
Re-execution of instruction n
TLB miss (instruction n + 1)
2
3
Re-execution of instruction n + 1
RIE (instruction n + 2)
IF = Instruction fetch
ID = Instruction decode
EX = Instruction execution
MA = Memory access
WB = Write back
Figure 4.2 Example of Acceptance Order of General Exceptions
All exceptions other than a reset are detected in the pipeline ID stage, and accepted at instruction
boundaries. However, an exception is not accepted between a delayed branch instruction and the
delay slot. A re-execution type exception detected in a delay slot is accepted before execution of
the delayed branch instruction. A completion type exception detected in a delayed branch
Rev. 5.00, 09/03, page 89 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
