Table 4.2 Exception Event Vectors
Exception Current
Exception Vector
Vector
Offset
Priority 1 Order
Address
*
Type
Instruction Exception Event
Reset
Aborted
Power-on reset
Manual reset
UDI reset
1
1
1
2
—
—
—
1
H'A00000000 —
H'A00000000 —
H'A00000000 —
General
Aborted
CPU address error
—
H'00000100
exception and retried (instruction access)
events
TLB miss
2
2
2
3
—
—
H'00000400
H'00000100
TLB invalid
(instruction access)
TLB protection
violation (instruction
access)
2
4
—
H'00000100
General illegal
instruction exception
2
2
2
5
5
6
7
8
9
—
—
—
—
—
—
H'00000100
H'00000100
H'00000100
H'00000400
H'00000100
H'00000100
Illegal slot instruction
exception
CPU address error
(data access)
TLB miss (data access 2
not in repeat loop)
TLB invalid (data
access)
2
TLB protection
2
violation (data access)
Initial page write
2
2
10
5
—
—
H'00000100
H'00000100
Completed Unconditional trap
(TRAPA instruction)
2
*
User breakpoint trap
DMA address error
2
2
n
—
—
—
—
H'00000100
H'00000100
H'00000600
H'00000600
—
—
—
General
interrupt
requests
Completed Nonmaskable interrupt 3
3
*
External hardware
interrupt
4
3
*
UDI interrupt
4
—
—
H'00000600
Notes: 1. Priorities are indicated from high to low, 1 being the highest and 4 the lowest.
2. The user defines the break point traps. 1 is a break point before instruction execution
and 11 is a break point after instruction execution. For an operand break point, use 11.
3. Use software to specify relative priorities of external hardware interrupts and peripheral
module interrupts (see section 6, Interrupt Controller (INTC)).
Rev. 5.00, 09/03, page 87 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
