instruction or delay slot is accepted after execution of the delayed branch instruction. The delay
slot here refers either to the next instruction after a delayed unconditional branch instruction or to
the next instruction when a delayed conditional branch instruction is true.
4.2.4
Exception Codes
Table 4.3 lists the exception codes written to the EXPEVT register (for reset or general
exceptions) or the INTEVT and INTEVT2 registers (for general interrupt requests) to identify
each specific exception event.
Table 4.3 Exception Codes
Exception Type
Exception Event
Exception Code
H'000
Reset
Power-on reset
Manual reset
H'020
UDI reset
H'000
General exception events
TLB miss/invalid (read)
TLB miss/invalid (write)
Initial page write
H'040
H'060
H'080
TLB protection violation (read)
TLB protection violation (write)
CPU address error (read)
CPU address error (write)
Unconditional trap (TRAPA instruction)
Illegal general instruction exception
Illegal slot instruction exception
User breakpoint trap
H'0A0
H'0C0
H'0E0
H'100
H'160
H'180
H'1A0
H'1E0
H'5C0
H'1C0
H'5E0
DMA address error
General interrupt requests
Nonmaskable interrupt
UDI interrupt
External hardware interrupts:
IRL3–IRL0 = 0000
H'200
H'220
IRL3–IRL0 = 0001
Rev. 5.00, 09/03, page 90 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
