Bits 5 and 4—Instruction Access/Operand Access Select A (IDA1, IDA0): These bits specify
whether an instruction access cycle or an operand access cycle is used as the bus cycle in the
channel A break conditions.
Bit 5: IDA1
Bit 4: IDA0
Description
0
0
1
0
1
Condition comparison is not performed
Instruction access cycle is used as break condition
Operand access cycle is used as break condition
(Initial value)
1
Instruction access cycle or operand access cycle is used as
break condition
Bits 3 and 2—Read/Write Select A (RWA1, RWA0): These bits specify whether a read cycle or
write cycle is used as the bus cycle in the channel A break conditions.
Bit 3: RWA1
Bit 2: RWA0
Description
0
0
1
0
1
Condition comparison is not performed
Read cycle is used as break condition
Write cycle is used as break condition
(Initial value)
1
Read cycle or write cycle is used as break condition
Bits 6, 1, and 0—Operand Size Select A (SZA2–SZA0): These bits select the operand size of
the bus cycle used as a channel A break condition.
Bit 6: SZA2 Bit 1: SZA1 Bit 0: SZA0 Description
0
0
0
Operand size is not included in break conditions
(Initial value)
1
0
1
0
1
*
Byte access is used as break condition
Word access is used as break condition
Longword access is used as break condition
Quadword access is used as break condition
Reserved (cannot be set)
1
0
1
1
Reserved (cannot be set)
Note: *: Don’t care
Rev. 6.0, 07/02, page 780 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
