20.2.2 Break Address Register A (BARA)
Bit:
31
30
29
28
27
26
25
24
BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24
Initial value:
R/W:
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
23
22
21
20
19
18
17
16
BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16
Initial value:
R/W:
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
15
14
13
12
11
10
9
BAA9
*
8
BAA8
*
BAA15 BAA14 BAA13 BAA12 BAA11 BAA10
Initial value:
R/W:
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
BAA7
*
6
BAA6
*
5
BAA5
*
4
BAA4
*
3
BAA3
*
2
BAA2
*
1
BAA1
*
0
BAA0
*
Initial value:
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: *: Undefined
Break address register A (BARA) is a 32-bit readable/writable register that specifies the virtual
address used in the channel A break conditions. BARA is not initialized by a power-on reset or
manual reset.
Bits 31 to 0—Break Address A31 to A0 (BAA31–BAA0): These bits hold the virtual address
(bits 31–0) used in the channel A break conditions.
Rev. 6.0, 07/02, page 777 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
