NMI
Input control
–
4
4
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
TMU
RTC
Interrupt
request
Com-
parator
Priority
identifier
SCI
SR
SCIF
WDT
REF
I3 I2 I1 I0
CPU
DMAC
H-UDI
GPIO
IPR
ICR
IPRA–IPRD*1
INTPRI00*2
Bus interface
INTC
TMU: Timer unit
RTC: Realtime clock unit
SCI:
Serial communication interface
SCIF: Serial communication interface with FIFO
WDT: Watchdog timer
REF: Memory refresh controller section of the bus state controller
DMAC: Direct memory access controller
H-UDI: Hitachi user debug interface
GPIO: I/O port
ICR:
Interrupt control register
IPRA–IPRD: Interrupt priority registers A–D*1
INTPRI00: Interrupt priority level setting register 00*2
SR:
Status register
Notes: *1 IPRD is provided only in the SH7750S and SH7750R.
*2 INTPRI00 is provided only in the SH7750R.
Figure 19.1 Block Diagram of INTC
Rev. 6.0, 07/02, page 752 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
