欢迎访问ic37.com |
会员登录 免费注册
发布采购

HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
 浏览型号HD6417750SBP200的Datasheet PDF文件第736页浏览型号HD6417750SBP200的Datasheet PDF文件第737页浏览型号HD6417750SBP200的Datasheet PDF文件第738页浏览型号HD6417750SBP200的Datasheet PDF文件第739页浏览型号HD6417750SBP200的Datasheet PDF文件第741页浏览型号HD6417750SBP200的Datasheet PDF文件第742页浏览型号HD6417750SBP200的Datasheet PDF文件第743页浏览型号HD6417750SBP200的Datasheet PDF文件第744页  
Data Transfer Operations  
SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE and RE  
bits in SCSCR2 to 0, then initialize the SCIF as described below.  
When the transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making  
the change using the following procedure. When the TE bit is cleared to 0, SCTSR2 is initialized.  
Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR2, SCFTDR2, or  
SCFRDR2. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND  
flag in SCFSR2 has been set. TEND can also be cleared to 0 during transmission, but the data  
being transmitted will go to the mark state after the clearance. Before setting TE again to start  
transmission, the TFRST bit in SCFCR2 should first be set to 1 to reset SCFTDR2.  
When an external clock is used the clock should not be stopped during operation, including  
initialization, since operation will be unreliable in this case.  
Figure 16.6 shows a sample SCIF initialization flowchart.  
Rev. 6.0, 07/02, page 688 of 986  
 复制成功!