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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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1. Receive error handling and  
break detection: If a receive  
error occurs, read the ORER,  
PER, and FER flags in  
Start of reception  
Read ORER, PER, and FER flags  
in SCSSR1  
SCSSR1 to identify the error.  
After performing the  
appropriate error handling,  
ensure that the ORER, PER,  
and FER flags are all cleared to  
0. Reception cannot be  
Yes  
PER or FER  
or ORER = 1?  
resumed if any of these flags  
are set to 1. In the case of a  
framing error, a break can be  
detected by reading the value  
of the RxD pin.  
No  
Error handling  
Read RDRF flag in SCSSR1  
No  
2. SCI status check and receive  
data read : Read SCSSR1 and  
check that RDRF = 1, then read  
the receive data in SCRDR1  
and clear the RDRF flag to 0.  
RDRF = 1?  
Yes  
Read receive data in SCRDR1,  
and clear RDRF flag  
3. Serial reception continuation  
procedure: To continue serial  
reception, complete zero-  
clearing of the RDRF flag  
before the stop bit for the  
current frame is received. (The  
RDRF flag is cleared  
in SCSSR1 to 0  
No  
All data received?  
Yes  
automatically when the direct  
memory access controller  
(DMAC) is activated by an RXI  
interrupt and the SCRDR1  
value is read.)  
Clear RE bit in SCSCR1 to 0  
End of reception  
Figure 15.10 Sample Serial Reception Flowchart (1)  
Rev. 6.0, 07/02, page 630 of 986  
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