Start
bit
Data
Parity Stop Start
Data
Parity Stop
1
1
bit
bit bit
bit
bit
Serial
data
Idle state
(mark state)
0
D0
D1
D7 0/1
1
0
D0 D1
D7 0/1
1
TDRE
TEND
TXI interrupt
request
TXI interrupt
request
TEI interrupt
request
Data written to SCTDR1
and TDRE flag cleared to
0 by TXI interrupt handler
One frame
Figure 15.9 Example of Transmit Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Serial Data Reception (Asynchronous Mode): Figure 15.10 shows a sample flowchart for serial
reception.
Use the following procedure for serial data reception after enabling the SCI for reception.
Rev. 6.0, 07/02, page 629 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
