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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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In serial reception, the SCI operates as described below.  
1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal  
synchronization and starts reception.  
2. The received data is stored in SCRSR1 in LSB-to-MSB order.  
3. The parity bit and stop bit are received.  
After receiving these bits, the SCI carries out the following checks.  
a. Parity check: The SCI checks whether the number of 1-bits in the receive data agrees with  
the parity (even or odd) set in the O/( bit in SCSMR1.  
b. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the  
first is checked.  
c. Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data  
can be transferred from SCRSR1 to SCRDR1.  
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in  
SCRDR1.  
If a receive error is detected in the error check, the operation is as shown in table 15.11.  
Note: No further receive operations can be performed when a receive error has occurred. Also  
note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared  
to 0.  
4. If the EIO bit in SCSPTR1 is cleared to 0 and the RIE bit in SCSCR1 is set to 1 when the  
RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated.  
If the RIE bit in SCSCR1 is set to 1 when the ORER, PER, or FER flag changes to 1, a  
receive-error interrupt (ERI) request is generated. A receive-data-full request is always output  
to the DMAC when the RDRF flag changes to 1.  
Table 15.11 Receive Error Conditions  
Receive Error  
Abbreviation  
Condition  
Data Transfer  
Overrun error  
ORER  
Reception of next data is  
completed while RDRF flag  
in SCSSR1 is set to 1  
Receive data is not transferred  
from SCRSR1 to SCRDR1  
Framing error  
Parity error  
FER  
PER  
Stop bit is 0  
Receive data is transferred  
from SCRSR1 to SCRDR1  
Received data parity differs  
from that (even or odd) set  
in SCSMR1  
Receive data is transferred  
from SCRSR1 to SCRDR1  
Figure 15.11 shows an example of the operation for reception in asynchronous mode.  
Rev. 6.0, 07/02, page 632 of 986  
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