by the user. When connecting a slave for which the total duration of consecutive accesses exceeds
the refresh cycle, the design should provide for the bus to be released as soon as possible after
negation of the %$&. signal is detected.
13.3.13 Slave Mode
In slave mode, the bus is normally in the released state, and an external device cannot be accessed
unless the bus is acquired through execution of the bus arbitration sequence. In a reset, also, the
bus-released state is established and the bus arbitration sequence is started from the reset vector
fetch.
To acquire the bus, the slave device asserts (drives low) the %65(4 signal in synchronization
with the rising edge of the clock. The bus use permission %6$&. signal is sampled for assertion
(low level) in synchronization with the rising edge of the clock. When %6$&. assertion is
detected, the bus control signals and address bus are immediately driven at the negated level. The
bus cycle is started at the next rising edge of the clock. The last signal negated at the end of the
access cycle is synchronized with the rising edge of the clock. When the bus cycle ends, the
%65(4 signal is negated and the release of the bus is reported to the master. On the next rising
edge of the clock, the control signals are set to high-impedance.
In order for the slave mode processor to begin access, the %6$&. signal must be asserted for at
least two cycles.
For a slave access cycle in DRAM or synchronous DRAM, the bus is released on completion of
precharging, as in the case of the master.
Refresh control is left to the master mode device, and any refresh control settings made in slave
mode are ignored.
Do not use DRAM/synchronous DRAM RAS down mode in slave mode.
Synchronous DRAM mode register settings should be made by the master mode device. Do not
use the DMAC’s DDT mode in slave mode.
Rev. 6.0, 07/02, page 484 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
