13.3.11 Bus Arbitration
The SH7750 Series is provided with a bus arbitration function that grants the bus to an external
device when it makes a bus request.
There are three bus arbitration modes: master mode, partial-sharing master mode, and slave mode.
In master mode the bus is held on a constant basis, and is released to another device in response to
a bus request. In slave mode the bus is not held on a constant basis; a bus request is issued each
time an external bus cycle occurs, and the bus is released again at the end of the access. In partial-
sharing master mode, only area 2 is shared with external devices; slave mode is in effect for area
2, while for other spaces, bus arbitration is not performed and the bus is held constantly. The area
in the master mode chip to which area 2 in the partial-sharing master mode chip is allocated is
determined by an external circuit.
Master mode and slave mode can be specified by the external mode pins. Partial-sharing master
mode is entered from master mode by means of a software setting. See Appendix C, Mode Pin
Settings, for the external mode pin settings. In master mode and slave mode, the bus goes to the
high-impedance state when not being held. In partial-sharing master mode, the bus is constantly
driven, and therefore an external buffer is necessary for connection to the master bus. In master
mode, it is possible to connect an external device that issues bus requests instead of a slave mode
chip. In the following description, an external device that issues bus requests is also referred to as
a slave.
The SH7750 Series has two internal bus masters: the CPU and the DMAC. When synchronous
DRAM or DRAM is connected and refresh control is performed, refresh requests constitute a third
bus master. In addition to these are bus requests from external devices in master mode. If requests
occur simultaneously, priority is given, in high-to-low order, to a bus request from an external
device, a refresh request, the DMAC, and the CPU.
To prevent incorrect operation of connected devices when the bus is transferred between master
and slave, all bus control signals are negated before the bus is released. When mastership of the
bus is received, also, bus control signals begin driving the bus from the negated state. Since
signals are driven to the same value by the master and slave exchanging the bus, output buffer
collisions can be avoided.
Bus transfer is executed between bus cycles.
When the bus release request signal (%5(4) is asserted, the SH7750 Series releases the bus as
soon as the currently executing bus cycle ends, and outputs the bus use permission signal (%$&.).
However, bus release is not performed during multiple bus cycles generated because the data bus
width is smaller than the access size (for example, when performing longword access to 8-bit bus
width memory) or during a 32-byte transfer such as a cache fill or write-back. In addition, bus
release is not performed between read and write cycles during execution of a TAS instruction, or
between read and write cycles when DMAC dual address transfer is executed. When %5(4 is
Rev. 6.0, 07/02, page 480 of 986
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