Table 13.18 Relationship between Address and CE when Using PCMCIA Interface (cont)
Bus
Width
(Bits)
Access
Read/ Size
Odd/
1
*
Write (Bits)
Even IOIS16 Access CE2 CE1 A0
D15–D8
Invalid
D7–D0
Dynamic Read
8
Even
Odd
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
—
1
0
0
Read data
Invalid
bus
sizing
—
0
1
1
Read data
2
*
16
8
Even
Odd
—
0
0
0
Upper read data Lower read data
—
—
1
—
0
—
0
—
—
Write
Read
Even
Odd
—
Invalid
Write data
Write data
Invalid
—
0
1
1
16
8
Even
Odd
—
0
0
0
Upper write data Lower write data
—
—
1
—
0
—
0
—
—
Even
Odd
—
Invalid
Ignored
Invalid
Invalid
Invalid
—
Read data
Invalid
First
Second
First
Second
—
0
1
1
Odd
1
0
1
Read data
Lower read data
Upper read data
—
16
8
Even
Even
Odd
0
0
0
1
0
1
—
1
—
0
—
0
Write
Even
Odd
—
Invalid
Invalid
Invalid
Write data
Write data
Write data
First
Second
First
Second
—
0
1
1
Odd
1
0
1
16
Even
Even
Odd
0
0
0
Upper write data Lower write data
1
0
1
Invalid
—
Upper write data
—
—
—
—
Notes: *1 In 32-bit/64-bit/32-byte transfer, the above accesses are repeated, with address
incrementing performed automatically according to the bus width, until the transfer data
size is reached.
*2 PCMCIA I/O card interface only
Rev. 6.0, 07/02, page 447 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
