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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Notes on Changing the Burst Length (SH7750R Only): In the SH7750R, when synchronous  
DRAM is connected with a 32-bit memory bus, the burst length can be selected as either 4 or 8 by  
the setting of the SDBL bit of the BCR3 register. For more details, see the description of the  
BCR3 register.  
Burst Read  
Figure 13.43 is the timing chart of a burst-read operation with a burst length of 4. Following  
the Tr cycle, during which an ACTV command is output, a READ command is issued during  
cycle Tc1, and a READA command is issued four cycles later. During the Td1 to Td8 cycles,  
read data are accepted on the rising edges of the external command clock (CKIO). Tpc is the  
cycle used to wait for the auto-precharging, which is triggered by the READA command, to be  
completed in the synchronous DRAM. During this cycle, a new command for accessing the  
same bank cannot be issued. In this LSI, the number of Tpc cycles is determined by the setting  
of the TPC2 to TPC0 bits of MCR, and no command that operates on the synchronous DRAM  
may be issued during these cycles.  
Td3  
Td4  
Td8  
Tpc  
Tr  
Trw  
Tc1  
Tc2  
Tc3  
Tc4/Td1  
Td2  
Td5  
Td6  
Td7  
CKIO  
Bank  
Row  
Row  
Row  
Precharge-sel  
H/L  
H/L  
Address  
c1  
c5  
RD/  
DQMn  
D31–D0 (read)  
c1  
c2  
c3  
c4  
c5  
c6  
c7  
c8  
CKE  
DACKn  
(SA: IO memory)  
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.  
Figure 13.43 Basic Timing of Synchronous DRAM Burst Read (Burst Length = 4)  
Rev. 6.0, 07/02, page 438 of 986  
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