TRs1 TRs2 TRs3 TRs4
TRs5
Trc
Trc
Trc
CKIO
RD/
DQMn
D63–D0
CKE
Figure 13.41 Synchronous DRAM Self-Refresh Timing
Relationship between Refresh Requests and Bus Cycle Requests
•
If a refresh request is generated during execution of a bus cycle, execution of the refresh is
deferred until the bus cycle is completed. Refresh operations are deferred during multiple bus
cycles generated because the data bus width is smaller than the access size (for example, when
performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as
a cache fill or write-back, and also between read and write cycles during execution of a TAS
instruction, and between read and write cycles when DMAC dual address transfer is executed.
If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution
is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a
refresh is waiting to be executed, so that a new refresh request is generated, the previous
refresh request is eliminated. In order for refreshing to be performed normally, care must be
taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh
interval. When a refresh request is generated, the %$&. pin is negated (driven high).
Therefore, normal refreshing can be performed by having the %$&. pin monitored by a bus
master other than the SH7750 Series requesting the bus, or the bus arbiter, and returning the
bus to the SH7750 Series.
Rev. 6.0, 07/02, page 434 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
