In a synchronous DRAM cycle, the %6 signal is asserted for one cycle at the beginning of each
data transfer cycle that is in response to a READ or READA command. Data are accessed in
the following sequence: in the fill operation for a cache miss, the data between 64-bit
boundaries that include the missing data are first read by the initial READ command; after
that, the data between 16-bit boundaries data that include the missing data are read in a
wraparound way. The subsequently issued READA command reads the 16 bytes of data,
which is the remainder of the data between 32-byte boundaries, from the start of the 16-byte
boundary.
•
Burst Write
Figure 13.44 is the timing chart for a burst-write operation with a burst length of 4. In this LSI,
a burst write takes place when a 32-byte data transfer has occurred. In a burst-write operation,
subsequent to the Tr cycle, in which ACTV command output takes place, a WRIT command is
issued during the Tc1 cycle, and a WRITA command is issued four cycles later. During the
write cycle, write data is output together with the write command. With a write command that
includes an auto precharge, the precharge is performed on the relevant bank of the
synchronous DRAM on completion of the write command so no new command that accesses
the same bank can be issued until precharging is completed. For this reason, Trwl cycles,
which are a period of waiting for precharging to start after the write command, are added. This
is additional to the precharge-waiting cycle used in read access. These cycles delay the issuing
of new commands to the synchronous DRAM. The setting of the TRWL2 to TRWL0 bits of
MCR selects the number of Trwl cycles. The data between 16-byte boundaries is first
accessed, and the data between 32-byte boundaries are then written in a wraparound way.
DACK is asserted for two cycles before the data-write cycle.
Rev. 6.0, 07/02, page 439 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
