master other than the SH7750 Series requesting the bus, or the bus arbiter, and returning the
bus to the SH7750 Series.
TRr1 TRr2 TRr3 TRr4
TRr5
Trc
Trc
Trc
CKIO
A25–A0
RD/
D63–D0
Figure 13.25 DRAM Self-Refresh Cycle Timing
Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time
(at least 100 µs or 200 µs) during which no access can be performed be provided, followed by at
least the prescribed number (usually 8) of dummy CAS-before-RAS refresh cycles. As the bus
state controller does not perform any special operations for a power-on reset, the necessary power-
on sequence must be carried out by the initialization program executed after a power-on reset.
Rev. 6.0, 07/02, page 412 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
