Bit 26—Data pin Pullup Resistor Control (DPUP) (SH7750R only): Controls the pullup
resistance of the data pins (D63 to D0). It is initialized at a power-on reset. The pins are not pulled
up when access is performed or when the bus is released, even if the ON setting is selected.
Bit 26: DPUP
Description
0
1
Sets pullup resistance of data pins (D63 to D0) ON
Sets pullup resistance of data pins (D63 to D0) OFF
(Initial value)
Bit 25—Control Input Pin Pull-Up Resistor Control (IPUP): Specifies the pull-up resistor
status for control input pins (NMI, ,5/3–,5/6, %5(4, MD6/,2,649, 5'<). IPUP is initialized
by a power-on reset.
Bit 25: IPUP
Description
0
Pull-up resistor is on for control input pins (NMI, ,5/3–,5/6, %5(4,
MD6/,2,649, 5'<)
(Initial value)
1
Pull-up resistor is off for control input pins (NMI, ,5/3–,5/6, %5(4,
MD6/,2,649, 5'<)
Bit 24—Control Output Pin Pull-Up Resistor Control (OPUP): Specifies the pull-up resistor
status for control output pins (A[25:0], %6, &6Q, 5', :(Q, RD/:5, 5$6, 5$65, &(5$, &(5%,
5'5, RD/:55) when high-impedance. OPUP is initialized by a power-on reset.
Bit 24: OPUP
Description
0
Pull-up resistor is on for control output pins (A[25:0], %6, &6Q, 5', :(Q,
RD/:5, 5$6, 5$65, &(5$, &(5%, 5'5, RD/:55)
(Initial value)
1
Pull-up resistor is off for control output pins (A[25:0], %6, &6Q, 5', :(Q,
RD/:5, 5$6, 5$65, &(5$, &(5%, 5'5, RD/:55)
Bit 21—Area 1 SRAM Byte Control Mode (A1MBC): MPX interface has priority when an
MPX interface is set. This bit is initialized by a power-on reset.
Bit 21: A1MBC
Description
0
1
Area 1 SRAM is set to normal mode
Area 1 SRAM is set to byte control mode
(Initial value)
Rev. 6.0, 07/02, page 328 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
