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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Bit 31—Endian Flag (ENDIAN): Samples the value of the endian specification external pin  
(MD5) in a power-on reset by the 5(6(7 pin. The endian mode of all spaces is determined by this  
bit. ENDIAN is a read-only bit.  
Bit 31: ENDIAN  
Description  
0
In a power-on reset, the endian setting external pin (MD5) is low,  
designating big-endian mode  
1
In a power-on reset, the endian setting external pin (MD5) is high,  
designating little-endian mode  
Bit 30—Master/Slave Flag (MASTER): Samples the value of the master/slave specification  
external pin (MD7) in a power-on reset by the 5(6(7 pin. The master/slave status of all spaces is  
determined by this bit. MASTER is a read-only bit.  
Bit 30: MASTER  
Description  
0
In a power-on reset, the master/slave setting external pin (MD7) is high,  
designating master mode  
1
In a power-on reset, the master/slave setting external pin (MD7) is low,  
designating slave mode  
Bit 29—Area 0 Memory Type (A0MPX): Samples the value of the area 0 memory type  
specification external pin (MD6) in a power-on reset by the 5(6(7 pin. The memory type of area  
0 is determined by this bit. A0MPX is a read-only bit.  
Bit 29: A0MPX  
Description  
0
In a power-on reset, the external pin specifying the area 0 memory type  
(MD6) is high, designating the area 0 as SRAM interface  
1
In a power-on reset, the external pin specifying the area 0 memory type  
(MD6) is low, designating the area 0 as MPX interface  
Bits 28, 27, 26*, 23, 22, 16*, and 1—Reserved: These bits are always read as 0, and should only  
be written with 0.  
Note: * SH7750, SH7750S only.  
Rev. 6.0, 07/02, page 327 of 986  
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