15.3.2 Operation in Asynchronous Mode ....................................................................... 623
15.3.3 Multiprocessor Communication Function............................................................ 634
15.3.4 Operation in Synchronous Mode.......................................................................... 642
15.4 SCI Interrupt Sources and DMAC .................................................................................... 651
15.5 Usage Notes....................................................................................................................... 652
Section 16 Serial Communication Interface with FIFO (SCIF)............................. 657
16.1 Overview........................................................................................................................... 657
16.1.1 Features ................................................................................................................ 657
16.1.2 Block Diagram ..................................................................................................... 659
16.1.3 Pin Configuration................................................................................................. 660
16.1.4 Register Configuration ......................................................................................... 661
16.2 Register Descriptions ........................................................................................................ 661
16.2.1 Receive Shift Register (SCRSR2)........................................................................ 661
16.2.2 Receive FIFO Data Register (SCFRDR2)............................................................ 662
16.2.3 Transmit Shift Register (SCTSR2)....................................................................... 662
16.2.4 Transmit FIFO Data Register (SCFTDR2) .......................................................... 663
16.2.5 Serial Mode Register (SCSMR2)......................................................................... 663
16.2.6 Serial Control Register (SCSCR2)....................................................................... 665
16.2.7 Serial Status Register (SCFSR2).......................................................................... 668
16.2.8 Bit Rate Register (SCBRR2)................................................................................ 674
16.2.9 FIFO Control Register (SCFCR2)........................................................................ 675
16.2.10 FIFO Data Count Register (SCFDR2) ................................................................. 678
16.2.11 Serial Port Register (SCSPTR2)........................................................................... 679
16.2.12 Line Status Register (SCLSR2)............................................................................ 684
16.3 Operation........................................................................................................................... 685
16.3.1 Overview.............................................................................................................. 685
16.3.2 Serial Operation ................................................................................................... 686
16.4 SCIF Interrupt Sources and the DMAC ............................................................................ 697
16.5 Usage Notes....................................................................................................................... 698
Section 17 Smart Card Interface...................................................................................... 703
17.1 Overview........................................................................................................................... 703
17.1.1 Features ................................................................................................................ 703
17.1.2 Block Diagram ..................................................................................................... 704
17.1.3 Pin Configuration................................................................................................. 705
17.1.4 Register Configuration ......................................................................................... 705
17.2 Register Descriptions ........................................................................................................ 706
17.2.1 Smart Card Mode Register (SCSCMR1) ............................................................. 706
17.2.2 Serial Mode Register (SCSMR1)......................................................................... 707
17.2.3 Serial Control Register (SCSCR1)....................................................................... 708
17.2.4 Serial Status Register (SCSSR1).......................................................................... 709
17.3 Operation........................................................................................................................... 710
Rev. 6.0, 07/02, page xxx of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
