Section 12 Timer Unit (TMU) ......................................................................................... 291
12.1 Overview........................................................................................................................... 291
12.1.1 Features ................................................................................................................ 291
12.1.2 Block Diagram ..................................................................................................... 292
12.1.3 Pin Configuration................................................................................................. 292
12.1.4 Register Configuration ......................................................................................... 293
12.2 Register Descriptions ........................................................................................................ 295
12.2.1 Timer Output Control Register (TOCR) .............................................................. 295
12.2.2 Timer Start Register (TSTR)................................................................................ 296
12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only)............................................... 297
12.2.4 Timer Constant Registers (TCOR)....................................................................... 298
12.2.5 Timer Counters (TCNT)....................................................................................... 298
12.2.6 Timer Control Registers (TCR)............................................................................ 299
12.2.7 Input Capture Register (TCPR2).......................................................................... 303
12.3 Operation........................................................................................................................... 304
12.3.1 Counter Operation................................................................................................ 304
12.3.2 Input Capture Function......................................................................................... 307
12.4 Interrupts ........................................................................................................................... 308
12.5 Usage Notes....................................................................................................................... 309
12.5.1 Register Writes..................................................................................................... 309
12.5.2 TCNT Register Reads .......................................................................................... 309
12.5.3 Resetting the RTC Frequency Divider ................................................................. 309
12.5.4 External Clock Frequency.................................................................................... 309
Section 13 Bus State Controller (BSC) ......................................................................... 311
13.1 Overview........................................................................................................................... 311
13.1.1 Features ................................................................................................................ 311
13.1.2 Block Diagram ..................................................................................................... 313
13.1.3 Pin Configuration................................................................................................. 314
13.1.4 Register Configuration ......................................................................................... 318
13.1.5 Overview of Areas ............................................................................................... 319
13.1.6 PCMCIA Support................................................................................................. 322
13.2 Register Descriptions ........................................................................................................ 326
13.2.1 Bus Control Register 1 (BCR1)............................................................................ 326
13.2.2 Bus Control Register 2 (BCR2)............................................................................ 335
13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only) ............................................... 337
13.2.4 Bus Control Register 4 (BCR4) (SH7750R Only) ............................................... 338
13.2.5 Wait Control Register 1 (WCR1)......................................................................... 340
13.2.6 Wait Control Register 2 (WCR2)......................................................................... 343
13.2.7 Wait Control Register 3 (WCR3)......................................................................... 351
13.2.8 Memory Control Register (MCR) ........................................................................ 352
13.2.9 PCMCIA Control Register (PCR)........................................................................ 359
13.2.10 Synchronous DRAM Mode Register (SDMR)..................................................... 362
Rev. 6.0, 07/02, page xxvii of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
