14.4.1 Examples of Transfer between External Memory and an External Device
with DACK .......................................................................................................... 544
14.5 On-Demand Data Transfer Mode (DDT Mode)................................................................ 545
14.5.1 Operation.............................................................................................................. 545
14.5.2 Pins in DDT Mode ............................................................................................... 547
14.5.3 Transfer Request Acceptance on Each Channel................................................... 550
14.5.4 Notes on Use of DDT Module ............................................................................. 571
14.6 Configuration of the DMAC (SH7750R).......................................................................... 574
14.6.1 Block Diagram of the DMAC .............................................................................. 574
14.6.2 Pin Configuration (SH7750R).............................................................................. 575
14.6.3 Register Configuration (SH7750R)...................................................................... 576
14.7 Register Descriptions (SH7750R) ..................................................................................... 579
14.7.1 DMA Source Address Registers 0–7 (SAR0–SAR7)........................................... 579
14.7.2 DMA Destination Address Registers 0–7 (DAR0–DAR7).................................. 579
14.7.3 DMA Transfer Count Registers 0–7 (DMATCR0–DMATCR7)......................... 580
14.7.4 DMA Channel Control Registers 0–7 (CHCR0–CHCR7) ................................... 580
14.7.5 DMA Operation Register (DMAOR)................................................................... 583
14.8 Operation (SH7750R)........................................................................................................ 586
14.8.1 Channel Specification for a Normal DMA Transfer ............................................ 586
14.8.2 Channel Specification for DDT-Mode DMA Transfer ........................................ 586
14.8.3 Transfer Channel Notification in DDT Mode ...................................................... 586
14.8.4 Clearing Request Queues by DTR Format........................................................... 587
14.8.5 Interrupt-Request Codes....................................................................................... 588
14.9 Usage Notes....................................................................................................................... 591
Section 15 Serial Communication Interface (SCI)..................................................... 593
15.1 Overview........................................................................................................................... 593
15.1.1 Features ................................................................................................................ 593
15.1.2 Block Diagram ..................................................................................................... 595
15.1.3 Pin Configuration................................................................................................. 596
15.1.4 Register Configuration ......................................................................................... 596
15.2 Register Descriptions ........................................................................................................ 597
15.2.1 Receive Shift Register (SCRSR1)........................................................................ 597
15.2.2 Receive Data Register (SCRDR1)........................................................................ 597
15.2.3 Transmit Shift Register (SCTSR1)....................................................................... 598
15.2.4 Transmit Data Register (SCTDR1) ...................................................................... 598
15.2.5 Serial Mode Register (SCSMR1)......................................................................... 599
15.2.6 Serial Control Register (SCSCR1)....................................................................... 601
15.2.7 Serial Status Register (SCSSR1).......................................................................... 605
15.2.8 Serial Port Register (SCSPTR1)........................................................................... 609
15.2.9 Bit Rate Register (SCBRR1)................................................................................ 613
15.3 Operation........................................................................................................................... 621
15.3.1 Overview.............................................................................................................. 621
Rev. 6.0, 07/02, page xxix of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
