Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
Status
Power-
Down
Mode
On-chip
On-Chip Peripheral
Entering
Conditions CPG
External
Memory
Exiting
Method
CPU
Memory
Modules
Pins
• Interrupt
• Reset
Sleep
SLEEP
Operating Halted
(registers
Held
Operating Held
Refreshing
instruction
executed
while STBY
bit is 0 in
STBCR
held)
• Interrupt
• Reset
Deep
sleep
SLEEP
Operating Halted
Held
Operating Held
(DMA
halted)
Self-
refreshing
instruction
executed
while STBY
bit is 0 in
STBCR,
(registers
held)
and DSLP
bit is 1 in
STBCR2
• Interrupt
• Reset
Standby
SLEEP
Halted
Halted
(registers
held)
Held
Halted*
Held
Self-
refreshing
instruction
executed
while STBY
bit is 1 in
STBCR
• Power-on
reset
Hardware Setting CA Halted
Halted
Undefined Halted*
High
impedance
Undefined
Refreshing
standby
pin low
(SH7750S,
SH7750R)
• Clearing
MSTP bit
to 0
Module
standby
Setting
MSTP bit
to 1 in
Operating Operating Held
Specified Held
modules
halted*
STBCR/
STBCR2
• Reset
Note: * The RTC operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock
(RTC)).
Rev. 6.0, 07/02, page 222 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
