Table 8.3 Execution Cycles (cont)
Instruc-
tion
Execu-
tion
Lock
Functional
Issue
Category
No. Instruction
210 FNEG
Group Rate Latency Pattern Stage Start Cycles
Double-
precision
floating-point
instructions
DRn
DRn
LS
FE
1
1
0
#1
—
F3
F1
F1
F1
F1
—
F1
—
F1
—
—
—
—
—
—
—
—
—
—
—
—
—
F1
—
—
F0
F1
—
2
—
22
3
211 FSQRT
(23, 24)/ #41
25
21
2
2
212 FSUB
213 FTRC
DRm,DRn
FE
FE
LS
CO
CO
CO
LS
CO
CO
CO
LS
LS
LS
LS
LS
LS
LS
LS
LS
FE
FE
FE
FE
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(7, 8)/9 #39
2
6
DRm,FPUL
Rm,FPUL
4/5
1
#38
#1
2
2
FPU system 214 LDS
—
3
—
3
control
215 LDS
instructions
Rm,FPSCR
@Rm+,FPUL
@Rm+,FPSCR
FPUL,Rn
4
#32
#2
216 LDS.L
217 LDS.L
218 STS
1/2
1/4
3
—
3
—
3
#33
#1
—
—
—
—
—
—
—
—
—
—
—
—
—
3
—
—
—
—
—
—
—
—
—
—
—
—
—
1
219 STS
FPSCR,Rn
FPUL,@-Rn
FPSCR,@-Rn
DRm,XDn
3
#1
220 STS.L
221 STS.L
1/1
1/1
0
#2
#2
Graphics
acceleration
instructions
222 FMOV
223 FMOV
224 FMOV
225 FMOV
226 FMOV
227 FMOV
228 FMOV
229 FMOV
230 FMOV
231 FIPR
#1
XDm,DRn
0
#1
XDm,XDn
0
#1
@Rm,XDn
@Rm+,XDn
@(R0,Rm),XDn
XDm,@Rn
XDm,@-Rm
XDm,@(R0,Rn)
FVm,FVn
2
#2
1/2
2
#2
#2
1
#2
1/1
1
#2
#2
4/5
1/4
1/4
#42
#36
#36
232 FRCHG
233 FSCHG
234 FTRV
—
—
2
—
—
4
XMTRX,FVn
(5, 5, 6, #43
7)/8
3
4
Notes: 1. See table 8.1 for the instruction groups.
2. Latency “L1/L2...”: Latency corresponding to a write to each register, including
MACH/MACL/FPSCR.
Example: MOV.B @Rm+, Rn “1/2”: The latency for Rm is 1 cycle, and the latency for
Rn is 2 cycles.
3. Branch latency: Interval until the branch destination instruction is fetched
Rev. 6.0, 07/02, page 218 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
