4. Conditional branch latency “2 (or 1)”: The latency is 2 for a nonzero displacement, and
1 for a zero displacement.
5. Double-precision floating-point instruction latency “(L1, L2)/L3”: L1 is the latency for FR
[n+1], L2 that for FR [n], and L3 that for FPSCR.
6. FTRV latency “(L1, L2, L3, L4)/L5”: L1 is the latency for FR [n], L2 that for FR [n+1], L3
that for FR [n+2], L4 that for FR [n+3], and L5 that for FPSCR.
7. Latency “L1/L2/L3/L4” of MAC.L and MAC.W instructions: L1 is the latency for Rm, L2
that for Rn, L3 that for MACH, and L4 that for MACL.
8. Latency “L1/L2” of MUL.L, MULS.W, MULU.W, DMULS.L, and DMULU.L instructions:
L1 is the latency for MACH, and L2 that for MACL.
9. Execution pattern: The instruction execution pattern number (see figure 8.2)
10.Lock/stage: Stage locked by the instruction
11.Lock/start: Locking start cycle; 1 is the first D-stage of the instruction.
12.Lock/cycles: Number of cycles locked
Exceptions:
1. When a floating-point computation instruction is followed by an FMOV store, an STS
FPUL, Rn instruction, or an STS.L FPUL, @-Rn instruction, the latency of the floating-
point computation is decreased by 1 cycle.
2. When the preceding instruction loads the shift amount of the following SHAD/SHLD, the
latency of the load is increased by 1 cycle.
3. When an LS group instruction with a latency of less than 3 cycles is followed by a
double-precision floating-point instruction, FIPR, or FTRV, the latency of the first
instruction is increased to 3 cycles.
Example: In the case of FMOV FR4,FR0 and FIPR FV0,FV4, FIPR is stalled for 2
cycles.
4. When MAC/MUL/DMUL is followed by an STS.L MAC, @-Rn instruction, the latency of
MAC/MUL/DMUL is 5 cycles.
5. In the case of consecutive executions of MAC/MUL/DMUL, the latency is decreased to
2 cycles.
6. When an LDS to MAC is followed by an STS.L MAC, @-Rn instruction, the latency of
the LDS to MAC is 4 cycles.
7. When an LDS to MAC is followed by MAC/MUL/DMUL, the latency of the LDS to MAC
is 1 cycle.
8. When an FSCHG or FRCHG instruction is followed by an LS group instruction that
reads or writes to a floating-point register, the aforementioned LS group instruction[s]
cannot be executed in parallel.
9. When a single-precision FTRC instruction is followed by an “STS FPUL, Rn” instruction,
the latency of the single-precision FTRC instruction is 1 cycle.
Rev. 6.0, 07/02, page 219 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
