Table 8.3 Execution Cycles (cont)
Instruc-
tion
Execu-
tion
Lock
Functional
Issue
Category
No. Instruction
119 NOP
120 CLRMAC
121 CLRS
122 CLRT
123 SETS
124 SETT
125 TRAPA
126 RTE
Group Rate Latency Pattern Stage Start Cycles
System
control
instructions
MT
CO
CO
MT
CO
MT
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
1
1
1
1
1
1
7
5
4
1
1
3
1
4
1
1
1
1
3
1
4
1
1
1
1
1
2
1
1
2
2
3
0
#1
—
—
3
—
2
3
#28
#1
F1
—
1
—
—
—
—
—
—
—
—
3
—
—
—
—
—
—
—
—
2
1
#1
—
1
#1
—
1
#1
—
#imm
7
#13
#8
—
5
—
127 SLEEP
128 LDTLB
129 LDC
4
#9
—
1
#2
—
Rm,DBR
3
#14
#15
#14
#16
#14
#14
#14
#17
#18
#17
#19
#17
#17
#17
#28
#28
#24
#29
#29
#25
#20
#21
SX
SX
SX
SX
SX
SX
SX
SX
SX
SX
SX
SX
SX
SX
F1
F1
SX
F1
F1
SX
—
130 LDC
Rm,GBR
3
3
2
131 LDC
Rm,Rp_BANK
Rm,SR
3
3
2
132 LDC
4
3
2
133 LDC
Rm,SSR
3
3
2
134 LDC
Rm,SPC
3
3
2
135 LDC
Rm,VBR
3
3
2
136 LDC.L
137 LDC.L
138 LDC.L
139 LDC.L
140 LDC.L
141 LDC.L
142 LDC.L
143 LDS
@Rm+,DBR
@Rm+,GBR
1/3
3/3
1/3
4/4
1/3
1/3
1/3
3
3
2
3
2
@Rm+,Rp_BANK CO
3
2
@Rm+,SR
@Rm+,SSR
@Rm+,SPC
@Rm+,VBR
Rm,MACH
Rm,MACL
Rm,PR
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
3
2
3
2
3
2
3
2
3
2
144 LDS
3
3
2
145 LDS
3
3
2
146 LDS.L
147 LDS.L
148 LDS.L
149 STC
@Rm+,MACH
@Rm+,MACL
@Rm+,PR
DBR,Rn
1/3
1/3
2/3
2
3
2
3
2
3
2
—
—
—
—
150 STC
SGR,Rn
3
—
Rev. 6.0, 07/02, page 215 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
