Table 8.3 Execution Cycles (cont)
Instruc-
tion
Execu-
tion
Lock
Functional
Issue
Category
No. Instruction
Group Rate Latency Pattern Stage Start Cycles
Fixed-point 63
DIV0U
DIV1
EX
EX
CO
CO
EX
CO
CO
CO
CO
CO
EX
EX
EX
EX
EX
EX
EX
1
1
2
2
1
2
2
2
2
2
1
1
1
1
1
1
1
4
1
1
1
4
5
1
1
3
1
1
4
1
#1
—
—
F1
F1
—
F1
F1
F1
F1
F1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
—
—
2
arithmetic
instructions
64
Rm,Rn
1
#1
65
66
67
68
69
70
71
72
73
74
75
76
77
DMULS.L Rm,Rn
DMULU.L Rm,Rn
4/4
#34
#34
#1
4/4
4
2
DT
Rn
1
—
4
—
2
MAC.L
MAC.W
MUL.L
@Rm+,@Rn+
@Rm+,@Rn+
Rm,Rn
2/2/4/4
#35
#35
#34
#34
#34
#1
2/2/4/4
4
2
4/4
4/4
4/4
1
4
2
MULS.W Rm,Rn
MULU.W Rm,Rn
4
2
4
2
NEG
NEGC
SUB
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
#imm,R0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
#1
1
#1
SUBC
SUBV
AND
1
#1
1
#1
Logical
instructions
78
79
80
81
82
83
84
85
86
87
88
89
90
91
1
#1
AND
1
#1
AND.B
NOT
#imm,@(R0,GBR) CO
4
#6
Rm,Rn
Rm,Rn
#imm,R0
EX
EX
EX
1
#1
OR
1
#1
OR
1
#1
OR.B
TAS.B
TST
#imm,@(R0,GBR) CO
4
#6
@Rn
CO
MT
MT
5
#7
Rm,Rn
#imm,R0
1
#1
TST
1
#1
TST.B
XOR
XOR
XOR.B
#imm,@(R0,GBR) CO
3
#5
Rm,Rn
EX
EX
1
#1
#imm,R0
1
#1
#imm,@(R0,GBR) CO
4
#6
Rev. 6.0, 07/02, page 213 of 986